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STA1050
CD-Audio one-chip
DATA BRIEF
Features

CD-R, CD-RW playback CLV (1x, 2x, 4x) & CAV mode (6x) 3.3V supply / 1.8V supply / 3.3V capable and 5V tolerant I/O Low power consumption at top speed (tbd) Power down mode Power On Reset / Brownout controller 33.8688MHz external quartz/resonator LQFP128 package Temperature range -40/+85C
LQFP128

Full range adjustment-free digital PLL EFM Demodulation and Synchronisation Q subcode & CD Text Decoder
Error Correction
Embedded ST7 Micro-controller
8-bit MCU with 4-stage pipeline 8.4672MHz clock with option up to 11.2896MHz 56Kbyte internal ROM (4Mb eFlash for debug) 4Kbytes internal RAM 2 I C master/slave interface (400 kHz) + 1 CRQ line
CIRC, capable of dual C1 and quadruple C2 erasure corrections jitter absorbing capacity 24 frames
Schock-Proof controller

Up to 64Mbit External SDRAM interface 4/8/16 bit data bus interface ADPCM (4:1) lossy compression for extended shock proof capability
Analogue Front-end Part
A, B, C, D, E, F voltage inputs Automatic gain and offset control for diode signals ALPC circuit for laser control with integrated Power MOS 8-bit 2channels general purpose ADC
Digital Interfaces

Digital Servo

Automatic fine gain/balance/offset adjustment for tracking and focus Embedded 16bit servo DSP (33.8688MHz) with programmable sampling rate 1.7Kx32 DSP program RAM 256x16 DSP coefficient RAM 256x16 DSP data RAM PDM actuator controls (Focus/Tracking/Spindle/Sledge) Embedded Stepping Sledge motor controller CLV & CAV spindle control Defect generator logic Digital Interpolator & Equalizer
I2S + EIAJ CP-340 output interface with slave mode capability (external clock) C2PO output SPDIF transmitter (IEC958) Soft audio mute/fade/attenuation De-emphasis filter I2S input for audio DAC if external audio processing (i.e. MP3 decoder) (or 3GPIOs) 8 dedicated GPIOs MLB interface for direct MOST
Audio Features
Digital Equalizer for bass/tremble control Built-in stereo DAC with 96 dB SNR De-emphasis filter built-in
Development Environment

Acquisition
On Chip ST7 Emulation (2 dedicated pins) C language compiler for ST7, Macro assembler, Linker, archiver, functional simulator Windows debugger
Order code
Part number STA1050 Package LQFP128 Packing Tube
November 2006
Rev 1
1/11
www.st.com 11
For further information contact your local STMicroelectronics sales office.
Contents
STA1050
Contents
1 2 3 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 System description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
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1
Figure 1.
STA1050
SDRAM I/F
MD Cross Interleaving Reed-Solomon CLV buffer Shock proof Memory controller Digital PLL Sync protection & EFM demodulator
Compress / Decompress
Block diagram
LD
Laser control
digital equalizer
Block diagram
ADC1 Subcode decoder
ADC2
AUX ADC
SPDIF/SONYLSI/I2S/MOST
fade/ mute/ deemph
+
master clock
DSP
ST7
56KB ROM 4KB RAM
I/V OFFSET GAIN ADC
A B C D E F A+C DECIM. + RATE defect TE FE JumpSpeed Track Loop filter Focus Loop filter SLED Loop filter B+D E F A+C B+D E F TrackCount 1.7Kx32 PRAM 256x16 XRAM 256x16 YRAM
PDM/ stepper
MS I2C I/F
PLL
DAC ANALOG filter
Spindle Motor Feedback(CAV)
observ/ debug I2S AUDIO in Focus Actuator Track Actuator Sled Motor Spindle Motor
AUDIO L/R out
Quartz/ Ceramic
GPIOs
Block diagram
3/11
Pin function description
STA1050
2
Table 1.
N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Pin function description
Pin List- LQFP128
Name DRD15/FLASH_D7 DRD0/GPC0 VDDPAD5 VDDPAD1 RESETN TESTEN I2C_SDA/GPB5 I2C_SCL/GPB4 I2C_CRQ #nc #nc PLL_VSS18P PLL_VDDA33P #nc PLL_XTI PLL_XTO #nc PLL_VDDA18P PLL_VDD18P FE_VSSA33S FE_A FE_C FE_B FE_D FE_E FE_F FE_VDDA33S FE_VDDPAD1 FE_ADCIN1 FE_ADCIN2 FE_VREF_ADC FE_VREF_OUT Description SDRAM Data 15 or FLASH Data 7 SDRAM Data 0 or ST7 GPIO PC0 3.3V 3.3V Hardware reset input (pull-up) Test enable signal (Active low) I2C I/F data or ST7 GPIO PB5 I2C I/F clock or ST7 GPIO PB4 I2C CRQ lime or ST7 GPIO PA0 to be connected to ground on PCB to be connected to ground on PCB PLL Digital&Analog ground PLL 3.3 Analog power supply to be connected to ground on PCB Crystal input Crystal output to be connected to ground on PCB PLL 1.8V Analog power supply PLL 1.8V Digital power supply Ground for servo channels OPU "A" input OPU "C" input OPU "B" input OPU "D" input OPU "E" input OPU "F" input 3.3V Analog for servo channels/ 3.3V for AFE pad ring (decoupling cap to Vssa) 3.3V for AFE pad ring General purpose ADC input 1 General purpose ADC input 2 General purpose ADC Vtop reference output External Vref Pickup (decoupling cap 1nF) Vdd Vdd Vss analog in analog in analog in analog in analog in analog in Vdd Vdd analog in analog in analog out analog out analog in analog out Vss Vdd Pin Type bidir, 3.3V, 2mA bidir, 3.3V, 2mA Vdd Vdd in, 3.3V in, 3.3V i2c dedicated i2c dedicated i2c dedicated
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STA1050 Table 1.
N 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67
Pin function description Pin List- LQFP128 (continued)
Name FE_VDDA33R FE_CEXT FE_REXT FE_VSSA33R FE_MD_LAS FE_CAP_LAS FE_LD_LAS FE_LD1_LAS FE_VDDPAD2 FE_VDDA33T FE_TESTP FE_TESTN FE_VSSA33T FE_VDDA18AD FE_VSSA18AD #nc FFSR #nc REFFSR SPDL SLED1 SLED2 ICC1/GPB6 ICC2/GPB7 VDD_TOP TFSR VSS_TOP VSSPAD1 VDDPAD2 VDDPAD3 ICD_N DRD4/FLASH_OE GPB0/CAV GPA7 GPA6 Description Analog 3.3V for Bandgap external cap for bandgap (1nF) external res for bandgap (25kOhm) Analog Ground Bandgap Laser driver input from monitor diode Laser driver compensation cap (30nF) First Laser driver output Second Laser driver output 3.3V for AFE pad ring Analog 3.3V for test buffer Test Buffer Positive Output Test Buffer Negative Output Analog Ground Test Buffer Analog 1.8V ADC Analog ground ADC to be connected to ground on PCB Focusing actuator control signal output - PDM to be connected to ground on PCB Clock (50% duty cycle) for Actuator PDM reference Spindle motor control signal output - PDM SLED motor control signal output1 (stepping/DC) - PDM SLED motor control signal output2 (stepping) -PDM Serial interface TX or ST7 GPIO PB6 Serial interface RX or ST7 GPIO PB7 Core VDD 1.8V Tracking actuator control signal output - PDM Core VSS Ground Pad Ring ground 3.3V for Digital Pad Ring 3.3V for Digital Pad Ring On-Chip-Emulator enable SDRAM Data 4 or FLASH Output Enable ST7 GPIO PB0 or CAV feedback input ST7 GPIO PA7 (external interrupt) ST7 GPIO PA6 bidir, 3.3V, 2mA bidir, 3.3V, 2mA bidir, 3.3V, 2mA bidir, 3.3V, 2mA bidir, 3.3V, 2mA bidir, 3.3V, 2mA Vdd bidir, 3.3V, 2mA Vss Vss Vdd Vdd in, 3.3V bidir, 3.3V, 2mA bidir, 3.3V, 2mA bidir, 3.3V, 2mA bidir, 3.3V, 2mA bidir, 3.3V, 2mA Pin Type Vdd analog analog Vss analog in analog analog out analog out Vdd Vdd analog out analog out Vss Vdd Vss
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Pin function description Table 1.
N 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 GPA5 GPA4 GPA3 GPA2/ICCDATA GPA1/ICCCLK VSS_TOP VSSPAD2 VDD_TOP MEMSEL0 SPDIF VDDPAD4 C2PO SDI/MLBDATA/GPB3 WSIN/MLBSIG/GPB2 SCKIN/MLBCLK/GPB1 LRCK/WSO MDAT/SDO BCLK/SCKO VSSPAD3 DRD5/FLASH_CE DRD7/FLASH_RSTN DRD6/FLASH_RYBY DRD8/FLASHD0 #nc ADAC_VDDA OUTR VMC OUTL ADAC_VSSA DRCLK DRD3/GPC3 DRA0/FLASHA0 VSSPAD4 DRCAS/FLASHA15 DRRAS/FLASHA14
STA1050
Pin List- LQFP128 (continued)
Name ST7 GPIO PA5 ST7 GPIO PA4 ST7 GPIO PA3 ST7 GPIO PA2 or ICC data for ST7 emulator ST7 GPIO PA1 or ICC clock for ST7 emulator Core VSS Ground Pad Ring ground Core VDD 1.8V Memory Select (ROM,FLASH) SPDIF Digital output 3.3V for Digital Pad Ring EIAJ CP-340 I/F C2PO I2S serial data input or MLB data line or ST7 GPIO PB3 I2S Word select input or MLB sig line or ST7 GPIO PB2 I2S Clk input or MLB clock line or ST7 GPIO PB1 EIAJ CP-340 I/F L/R signal or I2S Word Select output EIAJ CP-340 I/F dataout or I2S Data output EIAJ CP-340 I/F clk output or I2S Clock output Pad Ring ground SDRAM Data 5 or FLASH Chip Enable SDRAM Data 7 or FLASH Reset SDRAM Data 6 or FLASH Ready Busy SDRAM Data 8 or FLASH Data 0 to be connected to ground on PCB 3.3V Audio DAC Right channel analog output Common Mode input for audio DAC Left channel analog output Audio DAC ground SDRAM CLK SDRAM Data 3 or ST7 GPIO PC3 SDRAM Address 0 or Flash Address 0 Pad Ring ground SDRAM Col address sel or Flash Address 15 SDRAM Row address sel or Flash Address 14 Vdd analog out analog in analog out Vss out, 3.3V, 2mA bidir, 3.3V, 2mA out, 3.3V, 2mA Vss out, 3.3V, 2mA out, 3.3V, 2mA Description Pin Type bidir, 3.3V, 2mA bidir, 3.3V, 2mA bidir, 3.3V, 2mA bidir, 3.3V, 2mA bidir, 3.3V, 2mA Vss Vss Vdd in, 3.3V, pull-down bidir, 3.3V, 2mA Vdd bidir, 3.3V, 2mA bidir, 3.3V, 2mA bidir, 3.3V, 2mA bidir, 3.3V, 2mA bidir, 3.3V, 2mA bidir, 3.3V, 2mA bidir, 3.3V, 2mA Vss bidir, 3.3V, 2mA out, 3.3V, 2mA out, 3.3V, 2mA bidir, 3.3V, 2mA
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STA1050 Table 1.
N 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
Pin function description Pin List- LQFP128 (continued)
Name DRD14/FLASHD6 DRBA1/FLASHA13 DRBA0/FLASHA12 DRA11/FLASHA11 DRD13/FLASHD5 DRA10/FLASHA10 DRA9/FLASHA9 DRD12/FLASHD4 DRWR/FLASHA16 VDDPAD6 DRD11/FLASHD3 DRD2/GPC2 DRA8/FLASHA8 DRA7/FLASHA7 DRA6/FLASHA6 DRD10/FLASHD2 DRA5/FLASHA5 DRA4/FLASHA4 DRD9/FLASHD1 DRA3/FLASHA3 DRA2/FLASHA2 DRD1/GPC1 DRCLKE/FLASH_WEN VSSPAD5 DRA1/FLASHA1 APAD16 Description SDRAM Data 14 or Flash Data 6 SDRAM Bank sel address 1 or Flash Address 13 SDRAM Bank sel address 0 or Flash Address 12 SDRAM Address 11 or Flash Address 11 SDRAM Data 13 or Flash Data 5 SDRAM Address 10 or Flash Address 10 SDRAM Address 9 or Flash Address 9 SDRAM Data 12 or Flash Data 4 SDRAM Write control or Flash Address 16 3.3V for Digital Pad Ring SDRAM Data 11 or Flash Data 3 SDRAM Data 2 or ST7 GPIO PC2 SDRAM Address 8 or Flash Address 8 SDRAM Address 7 or Flash Address 7 SDRAM Address 6 or Flash Address 6 SDRAM Data 10 or Flash Data 2 SDRAM Address 5 or Flash Address 5 SDRAM Address 4 or Flash Address 4 SDRAM Data 9 or Flash Data 1 SDRAM Address 3 or Flash Address 3 SDRAM Address 2 or Flash Address 2 SDRAM Data 1 or ST7 GPIO PC1 SDRAM CLK enable or Flash Write Enable Pad Ring ground SDRAM Address 1 or Flash Address 1 Flash Address 17 Pin Type bidir, 3.3V, 2mA out, 3.3V, 2mA out, 3.3V, 2mA out, 3.3V, 2mA bidir, 3.3V, 2mA out, 3.3V, 2mA out, 3.3V, 2mA bidir, 3.3V, 2mA out, 3.3V, 2mA Vdd bidir, 3.3V, 2mA bidir, 3.3V, 2mA out, 3.3V, 2mA out, 3.3V, 2mA out, 3.3V, 2mA bidir, 3.3V, 2mA out, 3.3V, 2mA out, 3.3V, 2mA bidir, 3.3V, 2mA out, 3.3V, 2mA out, 3.3V, 2mA bidir, 3.3V, 2mA out, 3.3V, 2mA Vss out, 3.3V, 2mA in, 3.3V
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System description
STA1050
3
Figure 2.
System description
Complete CD Module application
Spindle Motor Sled Laser OPU Sled Motor
33.8688MHz
SDRAM (up to 64Mbit)
A, B, C, D, E, F LD/MD
SDRAM Controller
SPDIF I2Sout
Digital Outputs Digital Inputs (from Compr . Audio Proc.) Audio Out L/R HOST uP System Monitoring
STA1050
LQFP128 (ROM or FLASH)
I2Sin ANALOG AUDIOOUT I2C
Motor Driver IC
(Spindle, Focus,Tracking, Sledge, Tray)
PDM / STEPPING
Temp Sensor
AUX ADC GPIOs RST
RS232
STA1050 is an high integration, high performance chip which integrates most required components for CD module application. The only external components needed are: - - - a ceramic oscillator with a nominal frequency of 33.8688 MHz. All frequencies needed in STA1050 are internally synthesised thanks to a PLL. a motor driver IC to drive focus, tracking, spindle, sledge and tray motors a SDRAM to implement shock-proof handling (if needed)
STA1050 includes an embedded 8-bit CPU (ST7) running from an internal ROM (or Flash for debug) Program memory. The laser diode is driven directly using an embedded power PMOS. 2 analog inputs and 8GPIOs are available to monitor sensors and switches or to control auxiliary circuitry. An embedded Audio DAC generates a stereo audio output. This DAC can use as input a digital stream received by the I2Sin interface from an external source, for example a compressed audio processor. Several digital outputs are available: SPDIF, I2S, EIAJ and a MLB (Media Local Bus) interface which allows STA1050 to be directly interfaced to current and future MOST networks.
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STA1050
Package information
4
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 3. LQFP128 (14x14x1.4mm) Mechanical Data & Package Dimensions
mm DIM. MIN. A A1 A2 b c D D1 D3 e E E1 E3 L L1 K ccc 0.450 0.050 1.350 0.130 0.090 1.400 0.180 TYP. MAX. 1.600 0.150 1.450 0.230 0.200 0.002 0.053 0.005 0.003 0.630 0.551 0.488 0.016 0.630 0.551 0.488 0.750 0.018 0.024 0.0393 0.030 0.638 0.559 0.055 0.007 MIN. TYP. MAX. 0.063 0.006 0.057 0.009 0.008 0.638 0.559 inch
OUTLINE AND MECHANICAL DATA
15.800 16.000 16.200 0.622 13.800 14.000 14.200 0.543 12.400 0.400 15.800 16.000 16.200 0.622 13.800 14.000 14.200 0.543 12.400 0.600 1.000
0 (min.), 3.5 (typ.), 7(max.) 0.080 0.003
LQFP128 (14 x 14 x 1.40mm)
7111275 B
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Revision history
STA1050
5
Revision history
Table 2.
Date 21-Nov-2006
Document revision history
Revision 1 Initial release. Changes
10/11
STA1050
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